1. Field of the Invention
The invention relates to a formation of semiconductor devices, and more particularly to a process for forming a memory device.
2. Description of the Related Art
DRAM (dynamic random access memory), an important semiconductor device, conventionally comprises a plurality of memory cells comprising a cell array and a peripheral circuit electrically connected to the cell array. The memory cell carries one transistor and one capacitor. DRAM stores data by the charging of the capacitor of the memory cell.
With such increased integration the size of the memory cell and the transistor must be reduced to yield DRAM with higher memory capacity and higher processing speed. A 3D capacitor structure can itself reduce occupied area in the semiconductor substrate, such that the 3D capacitor, such as a deep trench capacitor, is applied in fabrication of DRAM of 64 MB and more. Conventional DRAM, with plane transistor, covers more of the semiconductor substrate and cannot satisfy the demand for high integration. Therefore, vertical transistors occupying less space have gained popularity in memory cell fabrication. Further, the memory cells are arranged in a checkerboard configuration, applied to 0.11 μm semiconductor process technology.
FIG. 1 is a cross-section of a DRAM comprising memory cells with side buried region. Referring to FIG. 1, the memory cell 100 comprises a buried region 102 on one side and an isolation layer on the other side. Further, the memory cell 100 further comprises a transistor 104. However, since the memory cell is less than 0.09 μm, electric leakage or short circuit can occur in the memory cell opposite to the buried region 102.